In relation to this: AMD released the Ryzen 9 7950X3D late last month, and despite some disagreements on its applicability in a 16-core CPU, it was ecstatic to see positive feedback for its second-generation 3D V-Cache. The technical information that explains its performance has now been shared.
AMD began blending nodes in 2019 when it used the 12nm node for the IO die of the Zen 2 microarchitecture and the 7nm node for the Core Complex Die (CCD) of the microarchitecture. Zen 4 will be upgraded to three nodes: the 5nm node for the CCD, the 6nm node for the IO die, and the 7nm node for the V-cache, AMD recently told Tom’s Hardware.
The eight cores and the CCD’s center are covered by the V-Cache.In a recent presentation at the ISSCC, AMD described some of the difficulties it encountered when stacking nodes on top of one another. To enable connection, the V caches on the 7950X3D and the original 5800X3D are placed above their ordinary L3 caches. Also, the configuration keeps the V-Cache away from the heat produced by the cores. On the 7950X3D, the V-cache overlaps with the L2 caches at the margins of the cores while on the 5800X3D it perfectly fits over the L3 cache.
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AMD boosted the size of each core’s L2 cache from 0.5MB to 1MB in Zen 3, which contributed to the issue.
The Zen 4 L2 cache is larger due to its larger capacity, but also because TSVs pass through it.
AMD has reduced the V-cache from 41mm2 to 36mm2 but kept the same 4.7B transistors. TSMC manufactures the cache on a new version of the 7nm node that it designed specifically for SRAM. As a result, the V-Cache has 32% more transistors per square millimeter than the CCD, even though the CCD is fabricated on the much smaller 5nm node.
All of the refinements and workarounds implemented by AMD add up to a 25% increase in bandwidth to 2.5 TB/s and an unspecified increase in efficiency. Not bad for nine months between the first and second generation of an additional chiplet. Hopefully it will show its worth when the Ryzen 7 7800X3D arrives in a month.
